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september 2013 doc id 15480 rev 7 1/26 1 L5300GJ 5 v low drop voltage regulator features operating dc supply voltage range 5.6 v to 40 v low dropout voltage 300 ma current capability low quiescent current very low consumption mode precision output voltage 5 v +/- 2% reset circuit sensing the output voltage programmable reset pulse delay with external capacitor early warning very wide stability range with low value output capacitor thermal shutdown and short circuit protection wide temperature range (t j = -40c to 150c) enable input for enabling / disabling the voltage regulator description L5300GJ is a low dropout linear regulator with microprocessor control functions such as power on reset, low voltage reset, early warning, on/off control. typical quiescent current is 55 a in very low output current mode and enabled regulator. it drops to 5 a with not enabled regulator. on-chip trimming results in high output voltage accuracy (2%). accuracy is kept over wide temperature range, line and load variation. early warning circuit monitors the input voltage and compares it with an internal voltage reference. the maximum input voltage is 40 v. the maximum output current is internally limited. internal temperature protection disables the voltage regulator output. in addition, only low value ceramic capacitor on output is required for stability (equal or above 220 nf). max dc supply voltage v s 40 v max output voltage tolerance v 0 +/-2% max dropout voltage v dp 500 mv output current i 0 300 ma quiescent current i qn 5 a (1) 55 a (2) 1. typical value with regulator disabled. 2. typical value with regulator enabled. powersso-12 table 1. device summary package order codes tube tape and reel powersso-12 L5300GJ L5300GJtr www.st.com
contents L5300GJ 2/26 doc id 15480 rev 7 contents 1 block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 powersso-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L5300GJ list of tables doc id 15480 rev 7 3/26 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 9. powersso-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
list of figures L5300GJ 4/26 doc id 15480 rev 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. output voltage vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. output voltage vs v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. output voltage vs v en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. drop voltage vs. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. current consumption vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 8. current consumption vs. output current (at light load condition). . . . . . . . . . . . . . . . . . . . . 10 figure 9. current consumption vs input voltage (i o = 0.1 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. current consumption vs input voltage (i o = 100 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. current limitation vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 12. current limitation vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13. short-circuit current vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 14. short-circuit current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 15. v en_high vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 16. v en_low vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 17. v rhth vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 18. v rlth vs t j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 19. v ewi_thh vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 20. v ewi_thl vs t j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 21. i cr vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 22. i dr vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 23. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 24. stability region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 25. maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 26. reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 27. early warning time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 28. powersso-12 pc board (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 29. rthj-amb vs. pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 18 figure 30. powersso-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 19 figure 31. thermal fitting model of vreg in in powersso-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 32. powersso-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 33. powersso-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 34. powersso-12 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L5300GJ block diagram and pins description doc id 15480 rev 7 5/26 1 block diagram and pins description figure 1. block diagram low voltage reset vs vo start - up voltage reference res vcr ew i ew o current limiter pow er driver thermal shutdow n gnd en vos low voltage reset vs vo start - up voltage reference res vcr ew i ew o current limiter pow er driver thermal shutdow n gnd en vos
block diagram and pins description L5300GJ 6/26 doc id 15480 rev 7 figure 2. configuration diagram (top view) table 2. pins description n name function 1 nc not connected 2r es reset output. internally connected to v o through a 20 k pull up resistor. this pin is pulled low when v o < v o_th . keep open if not needed 3v cr reset delay. connect an external capacitor between v cr pin and ground to adjust the reset delay time. keep open if not needed 4 gnd ground reference 5v os regulator output voltage sensing (connect to v o ) 6v o 5 v regulated output. block to gnd with a ceramic capacitor (c o 220 nf for regulator stability) 7v s supply voltage, block directly to gnd on the ic with a capacitor 8 nc not connected 9e n enable input. a high signal switches the regulator on. connect to v s if not needed 10 ew i early warning input. this pin monitors the v s voltage level through a resistor divider. connect to v s if not needed 11 nc not connected 12 ew o early warning output. internally connected to v o through 20 k pull up resistor. this pin is pulled low when ew i is below bandgap reference voltage. keep open if not needed -tab tab is connected to the substrate of the chip: connect to gnd or leave open (see figure 2 ). tab = substrate 9 8 7 6 1 3 4 2 5 10 11 12 nc r es v cr gnd v os v o v s nc e n ew i nc ew o
L5300GJ electrical specifications doc id 15480 rev 7 7/26 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the table 3: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.2 thermal data m table 3. absolute maximum ratings symbol parameter value unit v sdc dc supply voltage -0.3 to 40 v i vsdc input current internally limited v odc dc output voltage -0.3 to 6 v i vodc dc output current internally limited v od r es open drain output voltage r es -0.3 to v odc + 0.3 v i od r es open drain output current r es internally limited v od ewo open drain output voltage ew o -0.3 to v odc + 0.3 v i od e wo open drain output current ew o internally limited v cr v cr voltage -0.3 to v o + 0.3 v v ewi early warning input voltage -0.3 to 40 v v en enable input -0.3 to 40 v t j junction temperature -40 to 150 c v esd hbm esd hbm voltage level (hbm-mil std 883c) +/- 2 kv v esd cdm esd cdm voltage level (cdm aec-q100-011) +/- 750 v table 4. thermal data (1) 1. the values quoted are for pcb 77mm x 86 mm x 1.6mm, fr4, double layer with thermal vias (one copper heatsink layer, thickness 0.070 mm, area 8 cm 2 ). symbol parameter value unit r thj-case thermal resistance junction to case: powersso-12 8 k/w r thj-amb thermal resistance junction to ambient: powersso-12 48 k/w
electrical specifications L5300GJ 8/26 doc id 15480 rev 7 2.3 electrical characteristics values specified in this section are for v s = 5.6 v to 31 v, t j = -40c to 150c unless otherwise stated. table 5. general pin symbol parameter test condition min. typ. max. unit v o v o_ref output voltage v s = 8 v to 18 v; i o = 8 ma to 300 ma 4.9 5.0 5.1 v v o v o_ref output voltage v s = 5.6 v to 31v; i o = 8 ma to 300 ma 4.85 5.0 5.15 v v o v o_ref output voltage v s = 5.6 v to 31 v; i o = 0.1 ma to 8 ma 4.75 5.0 5.25 v v o i short short circuit current v s = 13.5 v 0.8 1.8 2.6 a v o i lim output current capability (1) 1. measured output current when the output voltage has dropped 100 mv from its nominal value obtained at 13.5 v and i o = 75 ma. v s = 13.5 v 0.6 1.6 2.5 a v s , v o v line line regulation voltage v s = 6 v to 28 v; i o = 60 ma 40 mv v o v load load regulation voltage v s = 13.5 v; i o = 8 ma to 300 ma; t j = 25 c 40 mv v s = 8 v to 18 v; i o = 8 ma to 300 ma 55 v s , v o v dp drop voltage (2) i o = 300 ma 500 mv v s , v o svr ripple rejection f r = 100 hz (3) 60 db v o i oth_h normal consumption mode output current 8ma v o i oth_l very low consumption mode output current 1.1 ma v o i oth_hyst output current switching threshold hysteresis v s = 13.5 v; t j = 25 c 0.8 ma v s , v o i qs current consumption with regulator disabled i qs = i vs ? i o v s = 13.5 v; e n = low 5 10 a v s , v o i qn_1 current consumption with regulator enabled i qn_1 = i vs ? i o v s = 13.5 v; i o = 0.1 ma to 1ma; e n = high 55 80 a v s , v o i qn_300 current consumption with regulator enabled i qn_300 = i vs ? i o v s = 13.5 v; i o = 300 ma; e n = high 34.2ma t w thermal protection temperature 150 190 c t w_hy thermal protection temperature hysteresis 10 c
L5300GJ electrical specifications doc id 15480 rev 7 9/26 2. v s - v o measured dropout when the output voltage has dropped 100 mv from its nominal value obtained at 13.5v and i o = 75 ma. 3. guaranteed by design. table 6. reset pin symbol parameter test condition min. typ. max. unit r es v res_l reset output low voltage r ext = 5 k ; v o >1v 0.4 v r es i res_lkg reset output high leakage current v res = v out 1a r es r res pull-up internal resistance versus v o 10 20 40 k r es v o_th v o out of regulation threshold v o decreasing 6 8 10 %below v o_ref v cr v rlth reset timing low threshold v s = 13.5 v 15 18 22 % v o_ref v cr v rhth reset timing high threshold v s = 13.5 v 47 50 53 % v o_ref v cr i cr charge current v s = 13.5 v 10 20 30 a v cr i dr discharge current v s = 13.5 v 10 20 30 a r es t rr reset reaction time 2 s r es t rd reset delay time v s = 13.5 v; c tr = 1 nf 2 4 6 ms table 7. early warning pin symbol parameter test condition min. typ. max. unit ew i e wi_th_low ew input low threshold voltage 2.35 2.50 2.65 v ew i e wi_th_high ew input high threshold voltage 2.42 2.57 2.72 v ew i e wi_th_hyst ew input threshold hysteresis 70 mv ew i i ewi_lkg ew input leakage current v ewi = 0 v; v s > 3 v -1 1 a ew o r ewo pull-up internal resistance versus v o 10 20 40 k ew o e wo_lv ew output low voltage (with external pull up) v ewi < 2.35 v; v s >4v; r ext =5k 400 mv ew o i wo ew output leakage v ewo = 5 v 1 a table 8. enable pin symbol parameter test condition min. typ. max. unit e n v en_low e n input low voltage 1 v e n v en_high e n input high voltage 3 v e n v en_hyst e n input hysteresis 500 mv e n i _leak pull-down current v en = 5 v 3 10 a
electrical specifications L5300GJ 10/26 doc id 15480 rev 7 2.4 electrical characteristics curves figure 3. output voltage vs t j figure 4. output voltage vs v s figure 5. output voltage vs v en figure 6. drop voltage vs. output current figure 7. current consumption vs. output current figure 8. current consumption vs. output current (at light load condition) 9rbuhi9 7m?& 9v 9 ,r p$ *$3*&)7 9rbuhi9 9v9 7f ?& ,r p$ *$3*&)7 9rbuhi 9 9hq9 9v 9 7f ? & *$3*&)7 *$3*&)7 9g s9 ,r p $ 7 l ? & 7 l ? & *$3*&)7 ,tq p$ ,rp$ 9v 9 (q +l j k 7m ?& *$3*&)7 ,tq p$ ,rp$ 9v 9 (q +ljk
L5300GJ electrical specifications doc id 15480 rev 7 11/26 figure 9. current consumption vs input voltage (i o = 0.1 ma) figure 10. current consumption vs input voltage (i o = 100 ma) figure 11. current limitation vs t j figure 12. current limitation vs input voltage figure 13. short-circuit current vs t j figure 14. short-circuit current vs input voltage ,t q?$ ,r p $ (q +ljk 7m ?& *$3*&)7 *$3*&)7 ,t qp $ ,r p $ (q + l j k 7m ?& *$3*&)7 ,o l p p $ 7m ?& 9v 9 *$3*&)7 ,o l p p $ 9v9 7m ?& 7m ?& *$3*&)7 ,vkr u w p $ 7m ?& 9v 9 *$3*&)7 ,vkr u w p $ 9v9 7m ?& 7m ?&
electrical specifications L5300GJ 12/26 doc id 15480 rev 7 figure 15. v en_high vs t j figure 16. v en_low vs t j figure 17. v rhth vs t j figure 18. v rlth vs t j figure 19. v ewi_thh vs t j figure 20. v ewi_thl vs t j *$3*&)7 9hqbkljk9 7m ?& 9v 9wr9 *$3*&)7 9hqborz 9 7m ?& 9v 9wr9 *$3*&)7 9ukw k9rbuhi 7m ?& 9v 9w r9 *$3*&)7 9uo w k9rbuhi 7m ?& 9v 9wr9 *$3*&)7 9h z l b w k k 9 7m ?& 9v 9wr 9 *$3*&)7 9hzl bw ko 9 7m ?& 9v 9w r9
L5300GJ electrical specifications doc id 15480 rev 7 13/26 figure 21. i cr vs t j figure 22. i dr vs t j *$3*&)7 ,fu?$ 7m ?& 9v 9w r9 *$3*&)7 ,gu?$ 7m ?& 9v 9w r9
application information L5300GJ 14/26 doc id 15480 rev 7 3 application information 3.1 voltage regulator the voltage regulator uses a p-channel mos transistor as a regulating element. with this structure a very low dropout voltage at current up to 300 ma is obtained. the output voltage is regulated up to input supply voltage of 40 v. the high-precision of the output voltage (2%) is obtained with a pre-trimmed reference voltage. the voltage regulator automatically adapts its own quiescent current to the output current level. in light load conditions the quiescent current goes down to 55 a only (low consumption mode). this procedure features a certain hysteresis on the output current (see figure 8 ). short-circuit protection to gnd and a thermal shutdown are provided. figure 23. application schematic the input capacitor c 1 100 f is necessary as backup supply for negative pulses which may occur on the line. the second input capacitor c 2 220 nf is needed when the c 1 is too distant from the v s pin and it compensates smooth line disturbances. the c 0 ceramic capacitor, connected to the output pin, is for bypassing to gnd the high-frequency noise and it guarantees stability even during sudden line and load variations. suggested value is c 0 =220nf ? with esr 100 m . stability region is reported in figure 24 . 9 %$77 /*- 567 9fu (:r (:l 9v *1' (q 9r & & 5 5 5 (: 5 (: ("1($'5
L5300GJ application information doc id 15480 rev 7 15/26 figure 24. stability region ? figure 25. maximum load variation response (652kp &r?) (65plq 67$%,/,7<5(*,21 817(67('5(*,21 *$3*36 note: the curve which describes the minimum esr is derived from characteriza tion data on the regulator with connected ceramic capacitors which feature lo w esr values (at 100 khz). any capacitor with further lower esr than the given plot value must be evaluated in each and every case. v o =50mv/div i o =100ma/div v s =13.5v i o =8 to 300ma t c =25c c o =220nf
application information L5300GJ 16/26 doc id 15480 rev 7 3.2 reset the reset circuit monitors the output voltage v o . if the output voltage becomes lower than v o_th then r es goes low with a delay time (t rr ). when the output voltage becomes higher than v o_th then r es goes high with a delay time t rd . this delay is obtained by 32 periods of oscillator. the oscillator period is given by: equation 1 t osc = [(v rhth - v rlth ) x c tr ] / i cr + [(v rhth - v rlth ) x c tr ] / i dr where: i cr = 20 a is an internally generated charge current, i dr = 20 a is an internally generated discharge current, v rhth = 2.5 v (typ) and v rlth = 0.95 v (typ) are two voltage thresholds, c tr is an external capacitor to be put between v cr pin and gnd. reset pulse delay t rd is given by: equation 2 t rd = 32 x t osc figure 26. reset time diagram 3.3 early warning this circuit compares the ew i input signal with the internal voltage reference (typically 2.5 v). the use of an external voltage divider makes the comparator very flexible in the application. this function can be used to supervise the supply input voltage either before or after the protection diode and to give additional information to the microprocessor such as low voltage warnings. v o v cr r es < t rr t rr t osc t rd = 32 tosc v out_th v rhth v rlth
L5300GJ application information doc id 15480 rev 7 17/26 figure 27. early warning time diagram 3.4 enable L5300GJ is also provided with an enable input, a high signal switches the regulator on. in standby mode the output is disabled and the current consumption of the device (quiescent current) is less than 10 a. t ewi t ewo ewi_th_high ewi_th_low high low
package and pcb thermal data L5300GJ 18/26 doc id 15480 rev 7 4 package and pcb thermal data figure 28. powersso-12 pc board (1) 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area = 77 mm x 86 mm, pcb thickness = 1.6 mm, cu thickness = 70 m (front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm, footprint dimension 4.1 mm x 6.5 mm ). figure 29. r thj-amb v s. pcb copper area in open box free air condition *$3*&)7 40 45 50 55 60 65 70 75 0246810 rthj_amb(c/ w) pcb cu heatsink area (cm^ 2)
L5300GJ package and pcb thermal data doc id 15480 rev 7 19/26 figure 30. powersso-12 thermal impedance junction ambient single pulse equation 3: pulse calculation formula where = t p /t figure 31. thermal fitting model of vreg in in powersso-12 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100 1000 time ( s) zth ( c/ w) footprint 8 cm 2 2 cm 2
package and pcb thermal data L5300GJ 20/26 doc id 15480 rev 7 table 9. powersso-12 thermal parameter area (cm 2 )footprint28 r1 (c/w) 1.2 r2 (c/w) 6 r3 (c/w) 7 r4 (c/w) 10 10 9 r5 (c/w) 22 15 10 r6 (c/w) 26 20 15 c1 (w.s/c) 0.0008 c2 (w.s/c) 0.0016 c3 (w.s/c) 0.05 c4 (w.s/c) 0.2 0.1 0.1 c5 (w.s/c) 0.27 0.8 1 c6 (w.s/c) 3 6 9
L5300GJ package and packing information doc id 15480 rev 7 21/26 5 package and packing information 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 powersso-12 mechanical data figure 32. powersso-12 package dimensions *$3*&)7
package and packing information L5300GJ 22/26 doc id 15480 rev 7 table 10. powersso-12 mechanical data symbol millimeters min. typ. max. a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k0o 8o x 2.200 2.800 y 2.900 3.500 ddd 0.100
L5300GJ package and packing information doc id 15480 rev 7 23/26 5.3 powersso-12 packing information figure 33. powersso-12 tube shipment (no suffix) figure 34. powersso-12 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a1.85 b6.75 c ( 0.1) 0.6 a c b base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
revision history L5300GJ 24/26 doc id 15480 rev 7 6 revision history table 11. document revision history date revision changes 09-aug-2007 1 initial release. 17-sep-2008 2 changed rev. numbering according with new ?target? standard. updated quiescent currents on features table. updated description on cover page. changed figure 1: block diagram . updated figure 2: configuration diagram (top view) : ? added pin names. updated table 2: pins description : ? changed pin 5 from nc to v os added values to table 4: thermal data . updated table 5.: general : ? updated test condition on v o_ref ? changed ishort values ? changed ilim values ? updated test condition on v line ? updated test condition on v load ? inserted i oth_h ? inserted i oth_l ? inserted i oth_hyst updated table 6: reset : ? updated test condition on v res_l ? updated test condition on v o_th ? changed v rlth values ? deleted test condition on t rr ? changed t rd values updated table 7: early warning : ? updated test condition on e wo_lv ? updated test condition on i wo updated table 8: enable : ? changed typ. value on v en_hyst ? updated test condition on i _leak updated chapter 3: application information ? deleted figure 3: behavior of output current versus regulated voltage v o ? updated section 3.2: reset ? updated section 3.4: enable added chapter 4: package and pcb thermal data . updated table 10: powersso-12 mechanical data : ? changed slug dimensions ?i o = 1 to 300 ma
L5300GJ revision history doc id 15480 rev 7 25/26 13-mar-2009 3 table 2: pins description ?v os : changed function table 6: reset ?i res_lkg : deleted v res = 5 v from test condition ?v o_th : deleted io = 1 ma to 300 ma from test condition ? v rlth : changed min/typ/max values ? t rd : changed min/typ/max values section 3.2: reset ? v rlth : changed coefficient section 3.4: enable ? replaced 5 a with10 a 07-dec-2009 4 updated corporate template (from v2 to v3) updated features list. updated figure 2: configuration diagram (top view) table 2: pins description ? added new row table 5: general ?i short : changed min/typ/max value ?i lim : changed min/typ/max value ?v line : changed test conditions ?v load : changed max value for vs = 8 v to 18 v, added new row table 6: reset ?v rlth : changed min/typ value table 8: enable ?i _leak : changed typ value section 3.3: early warning ? changed typical internal voltage reference value (from 1.23 v to 2.5 v) added section 2.4: electrical characteristics curves . updated chapter 3.1: voltage regulator . 27-jan-2012 5 updated figure 23: application schematic and figure 24: stability region . 07-feb-2012 6 modified figure 24: stability region on page 15 . 19-sep-2013 7 updated disclaimer. table 11. document revision history (continued) date revision changes
L5300GJ 26/26 doc id 15480 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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